A New Automatic VHDL Fault Injection Tool: A case studied

International audienceThe tools that are used to inject faults in FPGA based implementations are generally based in the modification of the VHDL code. In this work a new tool is presented. The main advantage of this new tool is that it is completely transparent to the programmer. The input of the tool is a VHDL description of the system under study and the output is the failure rate. All the steps required for the fault injection tests are performed in a completely automatic way, without the need of modifying the code. In this way, the VHDL programmer can concentrate in the design, and the final application can be tested with no extra effort