Reliability Limits of TMR Implemented in a SRAM-based FPGA: Heavy Ion Measures vs. Fault Injection Predictions

International audienceThis paper presents experimental results putting in evidence the potential weaknesses of a state-of-the-art fault tolerance strategy, the Triple Modular Redundancy (TMR), when implemented in SRAM-based FPGAs. HW/SW fault injection campaigns and accelerated radiation ground tests were performed to quantify the number of faults, Single Event Upsets (SEUs) required to obtain such critical failures