Performance evaluation of cryptographic algorithms in software and with hardware implementation of specialized instructions for the RISC-V instruction set architecture

The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in efficient implementation of common algorithms. While the algorithms can be implemented in software using the base instruction set of processors, there is considerable potential to reduce memory cost and improve speed using specialized instructions and associated hardware. However, there is a need to assess the relative benefits and costs of software implementations and new instructions that implement key cryptographic algorithms in fewer cycles. The primary aim of this thesis is to improve understanding of the cost of implementing cryptographic algorithms for the RISC-V instruction set architecture (ISA) for both implementations of the algorithms in software using the base RV32I instruction set and with implementation of instructions as hardware in additional functional units. RISC-V was designed a decade ago. Since then, the ISA has been improved and extended with new instruction sets, where the RISC-V cryptography instruction set extension is one of the upcoming instruction set extensions. This thesis provides hand-optimized RISC-V assembly language implementations of eleven cryptographic algorithms with and without the cryptography extension. For a cost-benefit analysis, a RISC-V processor with the cryptography extension is designed in hardware. Also, a new instruction is proposed to increase the implementation efficiency of the cryptography algorithms. The results show that software implementation requirements can change significantly according to algorithm and implementation method. Compared to implementations with only the base RV32I instruction set, implementations with the cryptography set extension provide 1.5X to 8.6X faster execution speed and 1.2X to 5.8X less program memory for five of the eleven algorithms