ISBN 978-1-4673-2355-0International audienceAn approach to study the effects of soft errors by fault injection in the VHDL model of a CPU (Control Processor Unit) is presented and illustrated by results obtained for a LEON3 processor. Experimental results are compared to those issued from a state-of-the-art method, the C.E.U. (Code Emulated Upsets). One of the advantages of the proposed method is the larger targeted SEU sensitive area leading to improved error rate predictions
International audienceIn this paper, a new methodology for the injection of single event upsets (SEU...
Modern processors embed features such as pipelined execution units and cache memories that can hardl...
This thesis deals with the design and validation of low-cost error detecting mechanisms that can be ...
International audienceThis paper describes two different but complementary approaches that can be us...
The Embedded system design is characterized by its daily complexity. It integrates a hardware and so...
International audienceThe probability of transient faults increases with the evolution of technologi...
International audienceThe Embedded system design is characterized by its daily complexity. It integr...
Abstract—An approach to study the effects of single event upsets (SEU) by fault injection performed ...
This paper proposes a high level technique to inject transient faults in processor-like circuits, an...
INTERNATIONAL STANDARD SERIAL NUMBERS (Translation and Original): 0923-8174The probability of transi...
International audienceEvaluating the sensitivity to soft-errors of integrated circuits and systems b...
ISBN :978-1-4020-5646-8This paper describes two different but complementary approaches that can be u...
International audienceThe miniaturization issues from the advanced integrated circuit manufacturing ...
Investigates an approach allowing one to evaluate the consequences of single event upset phenomena f...
In order to increase the robustness of a circuit against SEUs, fault injection is commonly used to l...
International audienceIn this paper, a new methodology for the injection of single event upsets (SEU...
Modern processors embed features such as pipelined execution units and cache memories that can hardl...
This thesis deals with the design and validation of low-cost error detecting mechanisms that can be ...
International audienceThis paper describes two different but complementary approaches that can be us...
The Embedded system design is characterized by its daily complexity. It integrates a hardware and so...
International audienceThe probability of transient faults increases with the evolution of technologi...
International audienceThe Embedded system design is characterized by its daily complexity. It integr...
Abstract—An approach to study the effects of single event upsets (SEU) by fault injection performed ...
This paper proposes a high level technique to inject transient faults in processor-like circuits, an...
INTERNATIONAL STANDARD SERIAL NUMBERS (Translation and Original): 0923-8174The probability of transi...
International audienceEvaluating the sensitivity to soft-errors of integrated circuits and systems b...
ISBN :978-1-4020-5646-8This paper describes two different but complementary approaches that can be u...
International audienceThe miniaturization issues from the advanced integrated circuit manufacturing ...
Investigates an approach allowing one to evaluate the consequences of single event upset phenomena f...
In order to increase the robustness of a circuit against SEUs, fault injection is commonly used to l...
International audienceIn this paper, a new methodology for the injection of single event upsets (SEU...
Modern processors embed features such as pipelined execution units and cache memories that can hardl...
This thesis deals with the design and validation of low-cost error detecting mechanisms that can be ...