Add to ORKGISBN 978-0-7685-4970-5International audienceAsynchronous designs are usually composed of conditional circuits. The analysis of these circuits is complex especially when delay variability is considered. In this paper, we design and implement a model-based Statistical Static Timing Analysis "SSTA" framework that is able to analyze conditional asynchronous circuits in efficient time. First, the paper introduces how the conditional circuits can be modeled; and then it shows how this model can be used to realize the SSTA analysis
systems, and the bounding which the clock provides, naturally leads to systems with worst case perfo...
The proposed project for the statistical static timing anal-ysis (SSTA) problem of latch-based seque...
UnrestrictedFor main stream acceptance of asynchronous circuits, a mature EDA tool flow is necessary...
An efficient and accurate statistical static timing analysis (SSTA) algorithm is reported in this wo...
The effect of process variation is getting worse with every technology generation. With variability ...
The 2018 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital S...
International audienceStatistical Static Timing Analysis (SSTA) is becoming necessary; but has not b...
As we are moving toward nanometre technology, the variability in the circuit parameters and operatin...
2011-10-03Static timing analysis (STA) is a key tool used for the design, optimization, and final si...
Accurate estimation of critical path delays in circuits is a challenging task, particularly when var...
Recent study shows that the existing first order canonical timing model is not sufficient to represe...
Abstract — This paper presents an adjustment-based modeling frame-work for Statistical Static Timing...
Abstract—To improve the accuracy of static timing analysis, the traditional nonlinear delay models a...
The move to deep submicron processes has brought about new problems that designers must contend with...
This brief presents an efficient approach to statistical static timing analysis (STA), which estimat...
systems, and the bounding which the clock provides, naturally leads to systems with worst case perfo...
The proposed project for the statistical static timing anal-ysis (SSTA) problem of latch-based seque...
UnrestrictedFor main stream acceptance of asynchronous circuits, a mature EDA tool flow is necessary...
An efficient and accurate statistical static timing analysis (SSTA) algorithm is reported in this wo...
The effect of process variation is getting worse with every technology generation. With variability ...
The 2018 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital S...
International audienceStatistical Static Timing Analysis (SSTA) is becoming necessary; but has not b...
As we are moving toward nanometre technology, the variability in the circuit parameters and operatin...
2011-10-03Static timing analysis (STA) is a key tool used for the design, optimization, and final si...
Accurate estimation of critical path delays in circuits is a challenging task, particularly when var...
Recent study shows that the existing first order canonical timing model is not sufficient to represe...
Abstract — This paper presents an adjustment-based modeling frame-work for Statistical Static Timing...
Abstract—To improve the accuracy of static timing analysis, the traditional nonlinear delay models a...
The move to deep submicron processes has brought about new problems that designers must contend with...
This brief presents an efficient approach to statistical static timing analysis (STA), which estimat...
systems, and the bounding which the clock provides, naturally leads to systems with worst case perfo...
The proposed project for the statistical static timing anal-ysis (SSTA) problem of latch-based seque...
UnrestrictedFor main stream acceptance of asynchronous circuits, a mature EDA tool flow is necessary...