International audienceIn this paper, we explain the validation of the Cache Analyzer prediction technique thanks to accelerated test experiments. The technique, described in one of our previous works and targeted towards end-user exploitation, focuses on the analysis of cache memory transactions. This paper presents the experimental setup, including the fault detection system used to detect errors in cache memories during the physical validation experiments, and to link them with application failures. We verified that our prediction tool would have correctly predicted the failures. Results obtained during neutron and proton irradiation tests are in accordance with the Cache Analyzer predictions
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
thorough reading and helpful comments. Authors also acknowledge Allen Sansano’s contribution in sett...
The traditional performance-cost benefits we have enjoyed for decades from technology scaling are ch...
International audienceStatic raw soft-error rates (SER) of COTS microprocessors are classically obta...
International audienceStatic raw soft-error rates (SER) of COTS microprocessors are classically obta...
Cosmic-ray induced soft errors in cache memories are becoming a major threat to the reliability of m...
International audienceThis paper presents two error models to evaluate safety of a software error de...
Technology scaling leads to burn-in phase out and increasing post-silicon test complexity, which inc...
Soft errors (also called transient errors, or single event upsets) are one of the vital errors that ...
2012-01-31Benchmarking the FIT (failures in time of 1E9 hours) rates of caches due to soft errors is...
International audienceStatic cache analysis characterizes a program’s cache behavior by determining ...
International audienceThis work evaluates the SEE static and dynamic sensitivityof a single-chip man...
Low voltage operation and small device sizes reduce the critical charge stored in a SRAM cell making...
AbstractAbstract interpretation is a technique for the static detection of dynamic properties of pro...
Instruction and data caches are well known architectural solutions that allow significantly improvin...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
thorough reading and helpful comments. Authors also acknowledge Allen Sansano’s contribution in sett...
The traditional performance-cost benefits we have enjoyed for decades from technology scaling are ch...
International audienceStatic raw soft-error rates (SER) of COTS microprocessors are classically obta...
International audienceStatic raw soft-error rates (SER) of COTS microprocessors are classically obta...
Cosmic-ray induced soft errors in cache memories are becoming a major threat to the reliability of m...
International audienceThis paper presents two error models to evaluate safety of a software error de...
Technology scaling leads to burn-in phase out and increasing post-silicon test complexity, which inc...
Soft errors (also called transient errors, or single event upsets) are one of the vital errors that ...
2012-01-31Benchmarking the FIT (failures in time of 1E9 hours) rates of caches due to soft errors is...
International audienceStatic cache analysis characterizes a program’s cache behavior by determining ...
International audienceThis work evaluates the SEE static and dynamic sensitivityof a single-chip man...
Low voltage operation and small device sizes reduce the critical charge stored in a SRAM cell making...
AbstractAbstract interpretation is a technique for the static detection of dynamic properties of pro...
Instruction and data caches are well known architectural solutions that allow significantly improvin...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
thorough reading and helpful comments. Authors also acknowledge Allen Sansano’s contribution in sett...
The traditional performance-cost benefits we have enjoyed for decades from technology scaling are ch...