IMPLEMENTING A STACK AS A DELAY-INSENSITIVE CIRCUIT

A case study in delay-insensitive circuit design is presented. A one bit wide stack is decomposed into an array of elements in a way that minimizes the response time of the stack to pushes and pops. The stack and element are specified in D-I Algebra and the correctness of the decomposition is proved by induction. The element is further decomposed delay-insensitively into Decision-Waits (generalizations of the Muller C-element) and XOR-gates.