This paper proposes the complete electrical design of a new multiply-by-two amplifier to be readily used in ultra high-speed medium resolution pipeline ADC stages. It is based in a switched-capacitor open-loop structure but with the novelty of having the gain accuracy improved by using an active amplifier with local feedback. Simulation results demonstrate that, with a very low-power dissipation and without employing any digital self-calibration or gain-control techniques, the circuit exhibits, over PVT corner and device mismatches, a dynamic performance and a gain-accuracy compatible with 6-bit level
This work mainly focuses on designing a low-power class-AB residue amplifier for a 12bit 500MS/sec p...
Residue amplification plays a key role in determining the energy efficiency, area and performance of...
The problems involved in the design of a transistor operational amplifier suitable for a repetitive ...
Abstract- A simple scheme for correcting the gain error of multiply-by-two gain amplifiers that are ...
15th International Conference on Mixed Design of Integrated Circuits and Systems, pp. 177 – 180, Poz...
IEEE International Symposium on Circuits and Systems, pp. 2258 – 2261, Seattle, EUAA low-power 1.2 V...
Analog-to-Digital converters (ADCs) are the basic and mandatory building block to link analog to dig...
Two side effects of technology scaling that have a significant impact on analog circuit design are t...
A new approach to achieve a switched-capacitor multiply-by-two gain-stage with reduced sensitivity t...
Graduation date: 2004Pipelined analog to digital converters (ADCs) are very important building\ud bl...
This report explain about the design of multiply-by-two amplifier for Analogue-To-Digital Converter....
A 16-bit pipelined analog-to digital device (ADC) is intended during this paper. The pipelined desig...
The scaling of CMOS technologies has increased the performance of general purpose processors and DSP...
Abstract- This paper proposes a novel finite-gain nonlinearity in MDACs of pipelined ADCs or poles a...
Among different analog-to-digital converter (ADC) architectures pipelined ADCs are the most suited f...
This work mainly focuses on designing a low-power class-AB residue amplifier for a 12bit 500MS/sec p...
Residue amplification plays a key role in determining the energy efficiency, area and performance of...
The problems involved in the design of a transistor operational amplifier suitable for a repetitive ...
Abstract- A simple scheme for correcting the gain error of multiply-by-two gain amplifiers that are ...
15th International Conference on Mixed Design of Integrated Circuits and Systems, pp. 177 – 180, Poz...
IEEE International Symposium on Circuits and Systems, pp. 2258 – 2261, Seattle, EUAA low-power 1.2 V...
Analog-to-Digital converters (ADCs) are the basic and mandatory building block to link analog to dig...
Two side effects of technology scaling that have a significant impact on analog circuit design are t...
A new approach to achieve a switched-capacitor multiply-by-two gain-stage with reduced sensitivity t...
Graduation date: 2004Pipelined analog to digital converters (ADCs) are very important building\ud bl...
This report explain about the design of multiply-by-two amplifier for Analogue-To-Digital Converter....
A 16-bit pipelined analog-to digital device (ADC) is intended during this paper. The pipelined desig...
The scaling of CMOS technologies has increased the performance of general purpose processors and DSP...
Abstract- This paper proposes a novel finite-gain nonlinearity in MDACs of pipelined ADCs or poles a...
Among different analog-to-digital converter (ADC) architectures pipelined ADCs are the most suited f...
This work mainly focuses on designing a low-power class-AB residue amplifier for a 12bit 500MS/sec p...
Residue amplification plays a key role in determining the energy efficiency, area and performance of...
The problems involved in the design of a transistor operational amplifier suitable for a repetitive ...