Characterization of 20-nm Node Ge2Sb2Te5 Phase-Change Memory using Simulation and I-V Modeling

MasterPhase-change memory (PCM) using chalcogenide materials has been spotlighted as non-volatile memory, which can fill the gap of memory hierarchy between DRAM and NAND Flash. However, as research on scaling down PCM devices has been actively conducted, problems such as resistance drift, cell-to-cell disturbance, undesired programming, and high RESET current have emerged. In particular, the chalcogenide material in the amorphous state has caused side effects, thereby raising the need for research for in nm-class PCM devices. Therefore, in this thesis, electrical and thermal performances of the PCM are characterized and discussed using technology computer-aided design (TCAD) and integrated circuit characterization and analysis program (IC-CAP) tools. Electrical and thermal performances of 20-nm node PCM described the bandgap model are extensively analysed according to physical parameters and geometry using fully-calibrated TCAD simulation. Increasing the maximal crystallization rate (r0) and decreasing the activation energy (Eact) reduces SET resistance and SET programming current, thus resistance ratio can be increased and consumes less power. This result suggests that Eact is more sensitive to electrical performance than r0. SET and RESET current decreases as impact ionization factor (II) increases. Also, programming current decreases and heat efficiency increases as thermal boundary resistance (TBR) thermal conductivity decreases and TBR metal resistivity increases. Decreasing the cell height reduces SET resistance, so increases read latency. However, current which produces the same Joule heating effect increases, thus increasing power consumption. Therefore, read latency and programming current are in a trade-off relationship when the cell height varies. Finally, these parameters can vary the threshold voltage, thus when designing the PCM cell, these parameters must be considered to meet the desired specifications. Threshold switching and snap-back mechanism is explained by the non-equilibrium carrier distribution and non-uniformity of electric field along the amorphous layer. Then, the appropriate barrier lowering change model that describe carrier transport in the subthreshold region is selected by comparing two models. Therefore, the subthreshold region, threshold switching, negative differential resistance, and ON region are implemented using analytical model of PCM. As a result, this model can be applied to circuit simulations of PCM devices with current equations based on physical computation