SRAM 비트 셀 기반 지능형 메모리 설계

DoctorThis dissertation presents three case studies on the design of smart SRAM that is capable of in-memory data processing in addition to the conventional SRAM read and write operations. The rst study introduces the design of a trans- posable 6-transistor (6T) SRAM macro, which provides high-speed read and write operations in both row- and column-wise directions to speed up online learning of neuromorphic processors at minimal area cost. The second study presents the design of a con gurable content-addressable memory (CAM) and SRAM macro, which performs both CAM and SRAM operations in a single 6T SRAM macro. The last study in this dissertation describes the design of an in-memory XNOR- network processing macro, which implements not only the XNOR-accumulation but also the calibration, batch normalization, and activation schemes in a 6T SRAM macro