A 7Gbps (160, 80) Non-Binary LDPC Decoder with Dual-Message EMS Algorithm in 22nm FinFET Technology

Non-binary low-density parity-check (NB-LDPC) codes, defined over GF(q), have been extensively studied since analyzed by Davey and Mackay in 1998 [1]. It was demonstrated that the NB-LDPC code has superior error-correcting performance than the binary counterparts in algorithm-level investigation. However, it is hard to directly employ a high-throughput NB-LDPC decoder due to its high processing complexity and excessively long decoding latency. Based on the conventional extended min-sum (EMS) algorithm [2], which reduces the message size without losing the correcting power, we introduce a high-throughput but area-efficient NB-LDPC decoder handling multiple message elements at the same time. The previous variable node processing (VNP) is modified to accept the multiple message elements and to promote parallel processing eventually. For the efficient decoder design, the delay overheads are carefully optimized in the two-stage sorter. The prototype decoder for the (160, 80) NB- LDPC code is implemented in a 22nm FinFET technology, achieving the decoding throughput of 7 Gbps.1