Monitoring setup and hold timing limits

International audienceFor safety or AVS applications purpose, it isimportant to validate and to monitor that the digital circuit isnever used outside its worst-case scenario for which it has beendesigned. Indeed, as there are many sources of static anddynamic variations (process, temperature, local mismatch,aging…), timing closure is performed to fulfil the functionalityat best case and worst-case corners. In-Situ Monitor approachare known to be good candidate to rise pre-error flag whencircuit operation point is very close to sign-off limits for setuptime violations. Here a new validation of this approach isproposed for hold time violations. Implemented on an AEScircuit, different experimental characterizations are presentedand comparison with Timing Analysis and SPICE simulationare given to illustrate the capability of the approach to detectsetup and hold time violation limits. Ageing of circuit exhibitssome variation in time of these limits. Finally, different use-casethat can affect the hold time violation are presented, and asfunction of the activity scenario, the slack for the path isdiscussed