This paper presents an application specific processor architecture for the calculation of simplicial piecewise linear functions of up to six dimensions with 24-bit wide input words. The architecture, in particular registers and bus connections, is specifically designed for the task of simplicial piecewise linear computation. The parameters of the function are stored in an external 16 MB RAM memory. A proof-of-concept integrated circuit (that achieved first silicon success) was fabricated through MOSIS in a 4 mm × 4 mm 0.5 μm standard CMOS process using an automated design flow based on Synopsys and Cadence tools and the OSU standard cell library.Fil: Rodríguez, Agustín Antonio. Consejo Nacional de Investigaciones Científicas y Técnicas. Cen...
International audienceThis article introduces several improvements to the multipartite method, a gen...
Abstract—This paper presents a programmable digital finite-impulse response (FIR) filter for high-pe...
AbstractWe describe the design and performance of the GRAPE-MP board, an SIMD accelerator board for ...
In this paper we present an integrated circuit implementing piecewise-linear (PWL) functions with th...
Neural Networks (NN) have been a matter of research because of their capability to solve complex pro...
This thesis is about implementing the functions for reciprocal, square root, inverse square root and...
This Letter presents the architecture implementation and testing of an single instruction multiple d...
139 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1988.The work presented in this th...
We present new algorithms for dynamic programming and transtivc closure which arc appropriate for v...
Piecewise polynomial interpolation is a well-established technique for hardware function evaluation....
In this paper we describe a bit-serial pipelined implementation of an inner product processor, and r...
The use of a special-purpose VLSI chip for solving a linear programming problem is presented. The ch...
This paper describes a design methodology to implement on FPGAs piecewise-affine (PWA) functions bas...
AbstractA profile is given of current research, as it pertains to computational mathematics, on Very...
Journal ArticleThis paper introduces a methodology for mapping algorithmic description into a concur...
International audienceThis article introduces several improvements to the multipartite method, a gen...
Abstract—This paper presents a programmable digital finite-impulse response (FIR) filter for high-pe...
AbstractWe describe the design and performance of the GRAPE-MP board, an SIMD accelerator board for ...
In this paper we present an integrated circuit implementing piecewise-linear (PWL) functions with th...
Neural Networks (NN) have been a matter of research because of their capability to solve complex pro...
This thesis is about implementing the functions for reciprocal, square root, inverse square root and...
This Letter presents the architecture implementation and testing of an single instruction multiple d...
139 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1988.The work presented in this th...
We present new algorithms for dynamic programming and transtivc closure which arc appropriate for v...
Piecewise polynomial interpolation is a well-established technique for hardware function evaluation....
In this paper we describe a bit-serial pipelined implementation of an inner product processor, and r...
The use of a special-purpose VLSI chip for solving a linear programming problem is presented. The ch...
This paper describes a design methodology to implement on FPGAs piecewise-affine (PWA) functions bas...
AbstractA profile is given of current research, as it pertains to computational mathematics, on Very...
Journal ArticleThis paper introduces a methodology for mapping algorithmic description into a concur...
International audienceThis article introduces several improvements to the multipartite method, a gen...
Abstract—This paper presents a programmable digital finite-impulse response (FIR) filter for high-pe...
AbstractWe describe the design and performance of the GRAPE-MP board, an SIMD accelerator board for ...