15 pagesInternational audienceAutomatic data transfer generation is a critical step for guided or automatic code generation for accelerators using distributed memories. Although good results have been achieved for loop nests, more complex control ows such as switches or while loops are generally not handled. This paper shows how to leverage the convex array regions abstraction to generate data transfers. The scope of this study ranges from inter-procedural analysis in simple loop nests with function calls, to inter-iteration data reuse optimization and arbitrary control ow in loop bodies. Generated transfers are approximated when an exact solution cannot be found. Array regions are also used to extend redundant load store elimination to arr...
this memo is a new loop analysis and transformation technique which brings compiler technology close...
Over the last decade, graphics processing units (GPUs) have seen their use broaden from purely graph...
The adoption of High-Level Synthesis (HLS) tools has significantly reduced accelerator design time. ...
Special Issue on LCPC'95 ; 29 pagesInternational audienceMany program optimizations require exact kn...
SIMD hardware accelerators o er an alternative to manycores when energy consumption and performance ...
Abstract. Many program optimizations require exact knowledge of the sets of array elements that are ...
This paper presents a technique for finding good distributions of arrays and suitable loop restructu...
2 pagesInternational audienceRecent compilers comprise an incremental way for converting software to...
International audienceWe build on prior work on intra-array memory reuse, for which a general theore...
International audienceIn this paper, we present original techniques for the generation and the effic...
International audienceIn this paper we concentrate on embedded parallel architectures with heterogen...
High Level Synthesis tools have reduced accelerator design time. However, a complex scaling problem ...
Loop vectorization, a key feature exploited to obtain high perfor-mance on Single Instruction Multip...
Abstract Many program optimizations require exact knowledge of the sets of array elements that are ...
Programming for parallel architectures that do not have a shared address space is extremely difficul...
this memo is a new loop analysis and transformation technique which brings compiler technology close...
Over the last decade, graphics processing units (GPUs) have seen their use broaden from purely graph...
The adoption of High-Level Synthesis (HLS) tools has significantly reduced accelerator design time. ...
Special Issue on LCPC'95 ; 29 pagesInternational audienceMany program optimizations require exact kn...
SIMD hardware accelerators o er an alternative to manycores when energy consumption and performance ...
Abstract. Many program optimizations require exact knowledge of the sets of array elements that are ...
This paper presents a technique for finding good distributions of arrays and suitable loop restructu...
2 pagesInternational audienceRecent compilers comprise an incremental way for converting software to...
International audienceWe build on prior work on intra-array memory reuse, for which a general theore...
International audienceIn this paper, we present original techniques for the generation and the effic...
International audienceIn this paper we concentrate on embedded parallel architectures with heterogen...
High Level Synthesis tools have reduced accelerator design time. However, a complex scaling problem ...
Loop vectorization, a key feature exploited to obtain high perfor-mance on Single Instruction Multip...
Abstract Many program optimizations require exact knowledge of the sets of array elements that are ...
Programming for parallel architectures that do not have a shared address space is extremely difficul...
this memo is a new loop analysis and transformation technique which brings compiler technology close...
Over the last decade, graphics processing units (GPUs) have seen their use broaden from purely graph...
The adoption of High-Level Synthesis (HLS) tools has significantly reduced accelerator design time. ...