A Multi-Level Design Methodology of Multistage Interconnection Network for MPSOCs

International audienceIn this paper, we propose a design methodology of Multistage Interconnection Networks (MINs) for multiprocessor system on chip. The framework covers the design step from algorithm level to RTL. We first develop a functional formalisation of MIN-based on-chip network at a high level of abstraction. The specification and the validation of the model have been defined in the logic of ACL2 proving system. The main objective in this step is to provide a formal description of the network that integrates architectural parameters, which have a huge impact on design costs. After validating the functional model, step 2 consists in the design and the implementation of the Delta multistage NoC dedicated to multiprocessor architectures on reconfigurable platforms FPGA. In the last step, we propose an evaluation methodology based on performance and cost metrics to evaluate different topologies of dynamic network through applications with different numbers of cores. We also show in the proposed framework that MIN will become future general-purpose communication architecture for MPSOCs