The switched-capacitor SAR architecture has benefited tremendously from technology scaling. We first present a charge-injection-based SAR architecture that shrinks the die area needed for a SAR ADC and achieves outstanding energy efficiency. We go on to discuss pipeline ADCs using SAR sub-ADCs and a ring amplifier. We present a SAR- assisted pipeline that achieves record efficiency for >12-bit pipeline ADCs. We argue that SAR ADCs are among the most efficient stand-alone converters for advanced nodes and an important building block for other converters
Low-power analog-to-digital converter (ADC) is a crucial part of wearable or implantable bioelectron...
Graduation date: 2014This dissertation presents two high-speed pipeline successive approximation ana...
textThe market for battery powered communications devices has grown significantly in recent years. T...
Abstract—Successive approximation register (SAR) ADC archi-tectures are popular for achieving high e...
Current trends constantly increase the need for ultra-low power solutions for the embedded and porta...
Successive Approximation (SAR) Analog-to-Digital Converters (ADCs) are among the most energy efficie...
Successive-approximation register analog-to-digital converters (SAR ADCs) have been around for a lon...
The conventional binary weighted array successive approximation register (SAR) analog-to-digital con...
This paper presents a 15-bit, two-stage pipelined successive approximation register analog-to-digita...
Analysis and experimental results for a new switching scheme and topology for charge sharing DACs us...
This paper presents a 14-bit, tunable bandwidth two-stage pipelined successive approximation analog ...
Graduation date: 2015Access restricted to the OSU Community, at author's request, from Dec. 12, 2014...
This thesis contains a review of published ring amplifier topologies. It is suggested to split the i...
A pipelined ADC is generally used for high speeds and high resolutions in applications where latency...
This paper presents a 7.9 fJ /conversion-step 10-bit 125 MS/s successive approximation register(SAR)...
Low-power analog-to-digital converter (ADC) is a crucial part of wearable or implantable bioelectron...
Graduation date: 2014This dissertation presents two high-speed pipeline successive approximation ana...
textThe market for battery powered communications devices has grown significantly in recent years. T...
Abstract—Successive approximation register (SAR) ADC archi-tectures are popular for achieving high e...
Current trends constantly increase the need for ultra-low power solutions for the embedded and porta...
Successive Approximation (SAR) Analog-to-Digital Converters (ADCs) are among the most energy efficie...
Successive-approximation register analog-to-digital converters (SAR ADCs) have been around for a lon...
The conventional binary weighted array successive approximation register (SAR) analog-to-digital con...
This paper presents a 15-bit, two-stage pipelined successive approximation register analog-to-digita...
Analysis and experimental results for a new switching scheme and topology for charge sharing DACs us...
This paper presents a 14-bit, tunable bandwidth two-stage pipelined successive approximation analog ...
Graduation date: 2015Access restricted to the OSU Community, at author's request, from Dec. 12, 2014...
This thesis contains a review of published ring amplifier topologies. It is suggested to split the i...
A pipelined ADC is generally used for high speeds and high resolutions in applications where latency...
This paper presents a 7.9 fJ /conversion-step 10-bit 125 MS/s successive approximation register(SAR)...
Low-power analog-to-digital converter (ADC) is a crucial part of wearable or implantable bioelectron...
Graduation date: 2014This dissertation presents two high-speed pipeline successive approximation ana...
textThe market for battery powered communications devices has grown significantly in recent years. T...