POWER AMPLIFIER IMPROVEMENT TECHNIQUES/CIRCUITS IN 0.35 μm SiGe HBT TECHNOLOGY FOR 5 GHz WIRELESS LAN BAND

In this thesis, a 5 GHz radio frequency power amplifier for IEEE 802.11a WLAN applications is designed, the ideas of on-chip power combining and using transmission lines as an RF on-chip choke are tested and layouts are drawn. The power amplifier employs SiGe HBT’s in AMS 0.35 μm BiCMOS process and it is designed to operate in Class A mode with a supply voltage of 3 Volts. Since the power amplifier is the final block and the final amplification stage of the transmitter chain in a wireless system, it must produce enough RF power to overcome the channel losses. At the same time, the power produced by the power amplifier should obey the power levels dictated by the operating standard. Therefore, in this work much consideration is given to design a power amplifier which provides enough output power for IEEE 802.11a WLAN standard. The power amplifier is designed to operate in Class A, and the bias points are chosen accordingly in order to preserve linearity. After the design of a single stage power amplifier, different versions of the circuit are designed and layouts are drawn. To decrease the dye area and the parasitic losses, the inductor which is used as the RF choke is replaced with capacitively loaded transmission lines. Moreover, in order to improve the linearity and obtain higher output power levels, two single stage power amplifiers are combined via on-chip Wilkinson power combiner made of lumped elements. Simulations are performed in ADS and Cadence environments in a parallel fashion