Characterization of Manifold Microchannel Heat Sinks During Two-Phase Operation

High-heat-flux removal is necessary for next-generation microelectronic systems to operate more reliably and efficiently. The direct embedding of microchannel heat sinks into the heated substrate serves to reduce the parasitic thermal resistances due to contact and conduction resistances typically associated with the attachment of a separate heat sink. Manifold microchannel (MMC) heat sinks can dissipate high heat fluxes at moderate pressure drops, especially during two-phase operation. High-aspect-ratio microchannels allow for a large enhancement in heat transfer area. This work focuses on designing intrachip MMC heat sinks for high-heat-flux dissipation and to characterize the flow morphology present in the MMCs during two-phase operation. A 3 × 3 array of heat sinks is fabricated into a heated silicon substrate for direct intrachip cooling. The heat sinks are fed in parallel using a hierarchical manifold distributor that is designed to deliver equal flow to each of the heat sinks. Each heat sink contains a bank of high-aspect-ratio microchannels; channels with nominal widths of 15 μm and 33 μm and nominal depths between 150 μm and 470 μm are tested. Discretizing the chip footprint area into multiple smaller heat sink elements with high-aspect-ratio microchannels ensures shortened effective fluid flow lengths. High two-phase fluid mass fluxes can thus be accommodated in micron-scale channels while keeping pressure drops low compared to traditional, microchannel heat sinks. The thermal and hydraulic performance of each heat sink array geometry is evaluated using the engineered dielectric liquid HFE-7100 as the working fluid and for mass fluxes ranging from 600 kg/m²s to 2100 kg/m²s at a constant inlet temperature of 59 °C. To simulate heat generation from electronics devices, a uniform background heat flux is generated with thin-film serpentine heaters fabricated on the silicon substrate opposite the channels; temperature sensors placed across the substrate provide spatially resolved surface temperature measurements. Experiments are also conducted with simultaneous background and hotspot heat generation; the hotspot heat flux is produced by an individual 200 μm × 200 μm hotspot heater. During uniform heating conditions, heat fluxes up to 1020 W/cm² are dissipated at chip temperatures less than 69 °C above the fluid inlet and at pressure drops less than 120 kPa. Heat sinks with wider channels yield higher wetted-area heat transfer coefficients, but not necessarily the lowest thermal resistance; for a fixed channel depth, samples with thinner channels can have increased total wetted areas owing to the smaller fin pitches. During simultaneous background and hotspot heating conditions, background heat fluxes up to 900 W/cm² and hotspot fluxes up to 2,700 W/cm² are dissipated. The hotspot temperature increases linearly with hotspot heat flux and is independent of background heat flux and mass flux. At hotspot heat fluxes of 2,700 W/cm², the hotspot experiences a temperature rise of 16 °C above the average chip temperature. The ability to fabricate and assemble a chip-integrated, compact hierarchical manifold used to deliver fluid to a 9 × 9 array of heat sinks has been demonstrated, with feature sizes significantly reduced compared to the 3 × 3 array of heat sinks. The integrated manifold provides ports to measure the pressure drop across the channel; combining these data with the overall pressure drop, the contributions of both components to the hydraulic performance is determined. The hierarchical manifold consists of eight feature layers that have a minimum feature size of 50 μm. The manifold is fabricated by etching one feature layer into each side of four silicon wafers and then thermocompression bonding the wafers together. The resulting manifold is a compact, leak-free device that is used to deliver fluid to the array of heat sinks and recollect the outlet flow from the heat sinks. A sample manifold was diced, revealing a manifold that was aligned with the channels within 5 μm. Heat fluxes up to 630 W/cm² are tested with temperatures and pressures reaching 110 °C and 135 kPa, respectively. An experiment is designed to provide simultaneous high-speed flow visualization and spatially-resolved wall temperature measurements on a single manifold microchannel. Visualizing the flow morphology inside the channel during two-phase operation is critical to being able to understand the performance MMCs. This work provides an understanding of the two-phase flow structure and wall temperature profiles in high-aspect-ratio microchannels, which cannot be extracted from the area- and time-averaged data obtained using the heat sinks containing many parallel channels. In high-aspect-ratio channels, vapor blanketing at the bottom of the channel is observed, which leads to significantly diminished thermal performance. The vapor formation characteristics in high-aspect-ratio microchannels also lead to time-periodic fluctuations that are not observed in low and intermediate aspect ratios. Opportunities for future experimental and model work to further understand flow boiling in MMCs are identified based on the work completed in this dissertation and the open literature