Integrated Neural Amplifiers Using DC Clamping Topology in 45 nm CMOS SOI

The neural recording systems have the potential to improve the understanding of central nervous system and may help curing neurological disease. With the increasing demands on neural recording systems, the requirements of low power and small area for such microelectronic systems increase. Devices are scaled down and different fabrication processes are introduced. The Global foundries 45 nm CMOS Silicon on Insulator (SOI) technology which uses a buried oxide to isolate the surface and substrate reduces the leakage current and improves the overall power consumption of the circuits. This thesis relates to design and characterization of the amplifiers for neural recording systems and all the ci rcuits are implemented in 45 nm SOI process. In this thesis, electrode electrolyte interface and the essential parameters are studied to implement the interface model. The design is based on these parameters and different DC clamping topologies, such as diode, NMOS, PMOS and poly resistance are presented. The proposed neural amplifiers improve the performance comparing with other reported clamping designs and addressed DC potential drifting issue at the recording interface