High performance cache mechanisms have a great impact on overall performance of computer systems by reducing memory-access latency. Least-Recently Used (LRU) mecha- nism can achieve good performance in small workload; how- ever, it suffers from thrashing caused by memory-intensive application. To address this challenge, dynamic insertion policy-DIP, which dynamically switches between LRU and an alternative policy, has recently been proposed. The algo- rithm, however, applies either one of the two policies to the entire cache based on the total number of misses. Therefore, such algorithm is not flexible enough to adjust to the differ- ent memory access pattern of each set. In this paper, we propose a novel approach, called SIP (Speculative ...
With the advent of chip-multiprocessors (CMPs), Thread-Level Speculation (TLS) remains a promising t...
An application’s cache miss rate is used in timing analysis, system performance prediction and ...
L1 data caches in high-performance processors continue to grow in set associativity. Higher associat...
Processor speed is improving at a faster rate than the speed of main memory, which makes memory acce...
Last-level cache performance has been proved to be crucial to the system performance. Essentially, a...
This work addresses the problem of the increasing performance disparity between the microprocessor a...
Many multi-core processors employ a large last-level cache (LLC) shared among the multiple cores. Pa...
With recent advances of processor technology, the LRU based shared last-level cache (LLC) has been w...
The inherent temporal locality in memory accesses is filtered out by the L1 cache. As a consequence,...
Caches mitigate the long memory latency that limits the performance of modern processors. However, c...
Abstract—We introduce Selfish-LRU, a variant of the LRU (least recently used) cache replacement poli...
Abstract—In modern processor systems, on-chip Last Level Caches (LLCs) are used to bridge the speed ...
Wire energy has become the major contributor to energy in large lower level caches. While wire energ...
Memory latency has become an important performance bottleneck in current microprocessors. This probl...
The performance gap between processors and main memory has been growing over the last decades. Fast ...
With the advent of chip-multiprocessors (CMPs), Thread-Level Speculation (TLS) remains a promising t...
An application’s cache miss rate is used in timing analysis, system performance prediction and ...
L1 data caches in high-performance processors continue to grow in set associativity. Higher associat...
Processor speed is improving at a faster rate than the speed of main memory, which makes memory acce...
Last-level cache performance has been proved to be crucial to the system performance. Essentially, a...
This work addresses the problem of the increasing performance disparity between the microprocessor a...
Many multi-core processors employ a large last-level cache (LLC) shared among the multiple cores. Pa...
With recent advances of processor technology, the LRU based shared last-level cache (LLC) has been w...
The inherent temporal locality in memory accesses is filtered out by the L1 cache. As a consequence,...
Caches mitigate the long memory latency that limits the performance of modern processors. However, c...
Abstract—We introduce Selfish-LRU, a variant of the LRU (least recently used) cache replacement poli...
Abstract—In modern processor systems, on-chip Last Level Caches (LLCs) are used to bridge the speed ...
Wire energy has become the major contributor to energy in large lower level caches. While wire energ...
Memory latency has become an important performance bottleneck in current microprocessors. This probl...
The performance gap between processors and main memory has been growing over the last decades. Fast ...
With the advent of chip-multiprocessors (CMPs), Thread-Level Speculation (TLS) remains a promising t...
An application’s cache miss rate is used in timing analysis, system performance prediction and ...
L1 data caches in high-performance processors continue to grow in set associativity. Higher associat...