Simple and accurate modeling of the 3D structural variations in FinFETs

Electrical EngineeringThe CMOS technology has encountered its limitations owing to aggressive scaling of the device feature size to improve circuit performance in the sub-wavelength lithography regime. Many new devices have been introduced in the beyond-Moore era. The FinFETs have been proposed for promising solution as a strong candidate for sub-32nm technology CMOS devices because of excellent immunity to short channel effect (SCE), low leakage current, high driving controllability and high output resistance. Moreover, the FinFET manufacturing process is compatible with the current CMOS process. The FinFETs comprise a fin-shaped body perpendicular to the wafer surface to carry the current. The fin is surrounded by the front and back gates or by a single gate, and its thickness is very small to geometrically minimize the short channel effect. Therefore, the small change in the thickness of the fin body has a significant effect on the electrical properties. The total width of the single-fin FinFET is fixed by the fin height (Hfin), discrete number of multi-fins structure is then used to generate wider (or stronger) devices. The driving current increases in the multiple fins but the capacitive coupling effects between neighboring fins will happen. The nature of 3-D fin structure is a good solution in terms of scaling down geometry and providing high driving currents. However, the 3-D fins structure inherently susceptible to geometry variations which result in inaccurate estimation of device property. Therefore, accurate but simple modeling approaches are required to identify the electrical property changes due to the 3D geometry variation of the FinFETs. In this thesis, the simple and accurate models are presented that can explain the property of FinFET by two 3D structural variations; First, the fin body thickness (Tsi) of the FinFET has a substantial effect on the device leakage, threshold voltage, and on-current variations. A number of TCAD (technology computer aided design) simulations of a double-gate SOI (silicon on insulator) FinFET structure with varying Tsi are performed and analyzed. The four different types of fin thickness variation models are designed to analyze the effect of Tsi variations on the device properties. It is shown that the conventional FinFET threshold voltage estimation method is not applicable in these cases of Tsi variation. Therefore, the additional threshold voltage estimation model is proposed to understand the Ion and Ioff variations owing to the fin body thickness variation along the gate channel. Also, the effects of the fin body variations on the inverter performance are analyzed by modulating the threshold voltage of the FinFET using the BSIM models. The simple and accurate Vth variation models are proposed to estimate the Ion and Ioff variations owing to the source-side Tsi variations. The proposed models match well with the simulation results, with errors less than 1.3% in Ion and 4.8% in Ioff. The analysis results indicate that Ion increases when the drain-side thickness increases and Ioff is reduced when the source-side thickness decreases. The optimal gate fin shape for achieving a higher operation speed with reduced leakage is obtained. This modified FinFET circuit configuration achieves leakage power savings of up to 30% and a penalty in delay by 1%. Second, the capacitance of the multi-fins FinFET depends on its structural and electrical characteristics. The device structure of the 32nm single gate multi-fins FinFET used to analyzed coupling capacitance for fin pitch (Pfin) and fin height (Hfin) variations. The coupling capacitance models of the multi-fins FinFET for fin pitch and fin height variations are proposed by using TCAD simulations. The proposed models are included in the circuit level verification by using of multi-fins FinFET inverters. These coupling capacitance models can be used to predict the transfer and input characteristics of the transistors, making the proposed models very useful for circuit design. There are significant effects by coupling capacitance when pitch and height of the fin change in the multiple fin structure. Increasing Pfin induces the reduction of Cc and reduction of Cg_total as well. As the Hfin increases, much higher impact on the Cc is identified. The proposed models match well with the simulation results, with 1.2% and 2.0% average errors by the Pfin and the Hfin, respectively. The capacitance and delay of the inverter are significantly impacted by the Pfin and the Hfin variations. By exploiting of the delay sensitivity to the area change (due to pitch between fins), optimum fin pitch is obtained in the 32nm FinFET.ope