Using a prime number N of memory banks on a vector processor allows a conflict-free access for any slice of N consecutive elements of a vector stored with a stride not multiple of N. To reject the use of such a prime number of memory banks, it is generally advanced that address computation for such a memory system would require systematic Euclidean Division by the prime number N. In this short note, we show that there exists a very simple mapping of data in the memory banks for which address compulations does not require any Euclidean Division
This paper introduces an innovative cache design for vector computers, called prime-mapped cache. By...
Operations on high-dimensional, fixed-width vectors can be used to distribute information from sever...
We discuss how much space is sufficient to decide whether a unary given number n is a pr...
Using a prime number N of memory banks on a vector processor allows a conflict-free access for any s...
IRISA - Publication interne no 644, 10 p., mars 1992SIGLEAvailable at INIST (FR), Document Supply Se...
International audience! Abstract Concurrent access to bank-interleaved memory structure have been st...
This paper presents a new abstract method for proving lower bounds in computational complexity. Base...
AbstractWe prove that polynomial time on a parallel random access machine (PRAM) with unit-cost mult...
On many commercial supercomputers, several vector register processors share a global highly interlea...
Memory allocation has been an active area of research. A large number of algorithms have been propos...
A physical memory address is no longer the stable concept it was. We demonstrate how modern computer...
Abstract—Modern high performance processors require memory systems that can provide access to data a...
We propose a new algorithm capable of partitioning a set of documents or other samples based on an e...
A memory architecture is presented. The memory architecture comprises a first memory and a second me...
A model of computation based on random access machines operating in parallel and sharing a common m...
This paper introduces an innovative cache design for vector computers, called prime-mapped cache. By...
Operations on high-dimensional, fixed-width vectors can be used to distribute information from sever...
We discuss how much space is sufficient to decide whether a unary given number n is a pr...
Using a prime number N of memory banks on a vector processor allows a conflict-free access for any s...
IRISA - Publication interne no 644, 10 p., mars 1992SIGLEAvailable at INIST (FR), Document Supply Se...
International audience! Abstract Concurrent access to bank-interleaved memory structure have been st...
This paper presents a new abstract method for proving lower bounds in computational complexity. Base...
AbstractWe prove that polynomial time on a parallel random access machine (PRAM) with unit-cost mult...
On many commercial supercomputers, several vector register processors share a global highly interlea...
Memory allocation has been an active area of research. A large number of algorithms have been propos...
A physical memory address is no longer the stable concept it was. We demonstrate how modern computer...
Abstract—Modern high performance processors require memory systems that can provide access to data a...
We propose a new algorithm capable of partitioning a set of documents or other samples based on an e...
A memory architecture is presented. The memory architecture comprises a first memory and a second me...
A model of computation based on random access machines operating in parallel and sharing a common m...
This paper introduces an innovative cache design for vector computers, called prime-mapped cache. By...
Operations on high-dimensional, fixed-width vectors can be used to distribute information from sever...
We discuss how much space is sufficient to decide whether a unary given number n is a pr...