A structural model for WCET estimation of Simple Out-of-Order Superscalar Processor

In the field of hard real time systems, there are two existing techniques to determine the worst-case execution time (WCET). The first techniques are based on measurements, and produce timing estimates, while the second ones consists in static analysis. However, both techniques are often inadequate to produce tight WCET estimates. As the predictions obtained throug measurement techniques are usually not guaranteed, the measurement based estimates can be wrong and, for static models, there is a lack of correspondence between those models and the given architectures. As a consequence, WCET estimates are often grossly overestimated. In this article, we provide a structural model for RISC superscalar microprocessors with out-of-order execution. Our goal is to establish this closer correspondence between the model and the architecture for the WCET calculation. To that effect, we have elaborated a validation methodology for the structural model which allows us to identify and quantify phenomena that produce deviations in order to refine the model with constraints