Predicate Diagrams for the Verification of Real-Time Systems

The original publication is available at www.springerlink.com ; Editeurs scientifiques Ranko Lazic and Rajagopal Nagarajan. Issue 19.3 of Formal Aspects of Computing contains selected papers arising from the Fifth International Workshop on Automated Verification of Critical Systems (AVoCS '05)International audienceThis article discusses a new format of predicate diagrams for the verification of real-time systems. We consider systems that are defined as extended timed graphs, a format that combines timed automata and constructs for modelling data, possibly over infinite domains. Predicate diagrams are succinct and intuitive representations of Boolean abstractions. They also represent an interface between deductive tools used to establish the correctness of an abstraction, and model checking tools that can verify behavioral properties of finite-state models. The contribution of this article is to extend the format of predicate diagrams to timed systems. We establish a set of verification conditions that are sufficient to prove that a given predicate diagram is a correct abstraction of an extended timed graph; these verification conditions can often be discharged with SMT solvers such as CVC-lite. Additionally, we describe how this approach extends naturally to the verification of parameterized systems. The formalism is supported by a toolkit, and we demonstrate its use at the hand of Fischer's real-time mutual-exclusion protocol