The presence of shared caches in current multicore processors may generate a lot of performance variability when several applications execute simultaneously. For the programmer of an application with quality-of-service goals, this performance variability may lead to a very pessimistic tuning. To solve this problem, there must be a way for the programmer to define a reasonable performance target and make sure that the actual performance is greater than or close to the target. We propose that the performance target be defined as the performancemeasured when each core runs a copy of the application, which we call self-performance. This study characterizes self-performance and explains how the shared-cache replacement policy can be modified for...
Performance metrics and models are prerequisites for scientific understanding and optimization. This...
International audienceMulti-core processors employ shared Last Level Caches (LLC). This trend will c...
International audienceThe use of multi-core architectures in real-time systems raises new issues reg...
The presence of shared caches in current multicore processors may generate a lot of performance vari...
The presence of shared caches in current multicore processors may generate a lot of performance vari...
International audienceAsymmetric coherency is a new optimisation method for coherency policies to su...
Reordering instructions and data layout can bring significant performance improvement for memory bou...
Replacement policies for shared caches on symmetric multicores: a programmer-centric point of view P...
An optimal replacement policy that minimizes the miss rate in a private cache was proposed several d...
Contention for shared cache resources has been recognized as a major bottleneck for multicores—espec...
The context of this work are performance models of software systems, which are used for predicting p...
The multicore revolution is underway, bringing new chips introducing more complex memory architectur...
International audienceMulti-core processors employ shared Last Level Caches (LLC). This trend will c...
It is clear that multicore processors have become the building blocks of today’s high-performance co...
Our thesis is that operating systems should manage the on-chip shared caches of multicore processors...
Performance metrics and models are prerequisites for scientific understanding and optimization. This...
International audienceMulti-core processors employ shared Last Level Caches (LLC). This trend will c...
International audienceThe use of multi-core architectures in real-time systems raises new issues reg...
The presence of shared caches in current multicore processors may generate a lot of performance vari...
The presence of shared caches in current multicore processors may generate a lot of performance vari...
International audienceAsymmetric coherency is a new optimisation method for coherency policies to su...
Reordering instructions and data layout can bring significant performance improvement for memory bou...
Replacement policies for shared caches on symmetric multicores: a programmer-centric point of view P...
An optimal replacement policy that minimizes the miss rate in a private cache was proposed several d...
Contention for shared cache resources has been recognized as a major bottleneck for multicores—espec...
The context of this work are performance models of software systems, which are used for predicting p...
The multicore revolution is underway, bringing new chips introducing more complex memory architectur...
International audienceMulti-core processors employ shared Last Level Caches (LLC). This trend will c...
It is clear that multicore processors have become the building blocks of today’s high-performance co...
Our thesis is that operating systems should manage the on-chip shared caches of multicore processors...
Performance metrics and models are prerequisites for scientific understanding and optimization. This...
International audienceMulti-core processors employ shared Last Level Caches (LLC). This trend will c...
International audienceThe use of multi-core architectures in real-time systems raises new issues reg...