Nowadays, on hierarchical shared memory multiprocessors with Non-Uniform Memory Access (NUMA), the number of cores accessing memory banks is considerably high. Such accesses produce more stress on the memory banks, generating load-balancing issues, memory contention and remote accesses. In this context, it is important to have a good understanding of memory access patterns and what are the inuences of data placement on such patterns. In this document, we have investigated memory accesses behavior of microbenchmarks and benchmarks over a ccNUMA platform with multi-core processors. Additionally, we have evaluated a set of memory policies that were used to place data among the machine memory banks. Our results have shown that an appropriate se...
This paper introduces two novel algorithms for thread migrations, named CIMAR (Core-aware Interchang...
International audienceModern multicore systems are based on a Non-Uniform Memory Access (NUMA) desig...
International audienceIn modern parallel architectures, memory accesses represent a common bottlenec...
Multi-core platforms with non-uniform memory access (NUMA) design are now a common resource in High ...
International audienceExploiting the full computational power of current hierarchical multiprocessor...
Multi-core nodes with Non-Uniform Memory Access (NUMA) are now a common architecture for high perfor...
Abstract—An important aspect of workload characterization is understanding memory system performance...
Les plates-formes multi-coeurs avec un accès mémoire non uniforme (NUMA) sont devenu des ressources ...
The latency of memory access times is hence non-uniform, because it depends on where the request ori...
Non-uniform memory access (NUMA) architectures are modern shared-memory, multi-core machines offerin...
International audienceNowadays, NUMA architectures are common in compute-intensive systems. Achievin...
Modern multicore systems are based on a Non-Uniform Memory Access (NUMA) design. In a NUMA system, c...
In scalable multiprocessor architectures, the times required for a processor to access various porti...
International audienceDynamic task-parallel programming models are popular on shared-memory systems,...
Cache Coherent Non-Uniform Memory Access (CC-NUMA) architectures have received strong interests from...
This paper introduces two novel algorithms for thread migrations, named CIMAR (Core-aware Interchang...
International audienceModern multicore systems are based on a Non-Uniform Memory Access (NUMA) desig...
International audienceIn modern parallel architectures, memory accesses represent a common bottlenec...
Multi-core platforms with non-uniform memory access (NUMA) design are now a common resource in High ...
International audienceExploiting the full computational power of current hierarchical multiprocessor...
Multi-core nodes with Non-Uniform Memory Access (NUMA) are now a common architecture for high perfor...
Abstract—An important aspect of workload characterization is understanding memory system performance...
Les plates-formes multi-coeurs avec un accès mémoire non uniforme (NUMA) sont devenu des ressources ...
The latency of memory access times is hence non-uniform, because it depends on where the request ori...
Non-uniform memory access (NUMA) architectures are modern shared-memory, multi-core machines offerin...
International audienceNowadays, NUMA architectures are common in compute-intensive systems. Achievin...
Modern multicore systems are based on a Non-Uniform Memory Access (NUMA) design. In a NUMA system, c...
In scalable multiprocessor architectures, the times required for a processor to access various porti...
International audienceDynamic task-parallel programming models are popular on shared-memory systems,...
Cache Coherent Non-Uniform Memory Access (CC-NUMA) architectures have received strong interests from...
This paper introduces two novel algorithms for thread migrations, named CIMAR (Core-aware Interchang...
International audienceModern multicore systems are based on a Non-Uniform Memory Access (NUMA) desig...
International audienceIn modern parallel architectures, memory accesses represent a common bottlenec...