Shared Data Caches Conflicts Reduction for WCET Computation in Multi-Core Architectures.

International audienceThe use of multi-core architectures in real-time systems raises new issues regarding the estimation of safe and tight worst-case execution times. Indeed, the sharing of hardware resources occurring on such architectures is a new source of indeterminism. Caches, as one of these shared assets, become harder to analyse; concurrent tasks may any time alter their contents. This paper presents a safe method to estimate conflicts stemming from data cache sharing and their integration in data cache analyses. The other, and foremost, contribution of this paper is the introduction of bypass heuristics to reduce these conflicts, allowing for reuse to be more easily captured by shared caches analysis