International audienceVideo decoding and image processing in embedded systems are subject to strong resource constraints, particularly in terms of memory. List-scheduling heuristics with static priorities (HEFT, SDC, etc.) being the oft-cited solutions due to both their good performance and their low complexity, we propose a method aimed at introducing the notion of memory into them. Moreover, we show that through appropriate adjustment of task priorities and judicious resort to insertion-based policy, speedups up to 20\% can be achieved. Lastly, we show that our technique allows to prevent deadlock and to substantially reduce the required memory footprint compared to classic list-scheduling heuristics.Le décodage vidéo et le traitement d'i...
International audienceScheduling in High-Performance Computing (HPC) has been traditionally centered...
The processor speeds continue to improve at a faster rate than the memory access times. The issue o...
Achieving optimal throughput by extracting parallelism in behavioral synthesis often exaggerates mem...
International audienceVideo decoding and image processing in embedded systems are subject to strong ...
International audienceTask scheduling is an important aspect for parallel programming. In this paper...
WOSInternational audienceModern embedded systems tend to use multiple cores or processors for proces...
International audienceThis paper deals with load balancing and efficient memory usage for homogeneou...
This report provides memory-aware heuristics to schedule tasks graphs onto heterogeneous resources, ...
Although numerous electronic devices are nowadays able to play video contents in real time and offer...
This paper presents a constructive algorithm for memory-aware task assignment and scheduling, which ...
International audienceA now-classical way of meeting the increasing demand for computing speed by HP...
Increasing interest in the high-volume high-performance embedded processor market motivates the stan...
Hardware accelerators, such as GPUs, now provide a large part of the computational power used for sc...
A now-classical way of meeting the increasing demand for computing speed by HPC applications is the ...
International audienceIn this paper, we present a new tri-criteria scheduling heuristic for scheduli...
International audienceScheduling in High-Performance Computing (HPC) has been traditionally centered...
The processor speeds continue to improve at a faster rate than the memory access times. The issue o...
Achieving optimal throughput by extracting parallelism in behavioral synthesis often exaggerates mem...
International audienceVideo decoding and image processing in embedded systems are subject to strong ...
International audienceTask scheduling is an important aspect for parallel programming. In this paper...
WOSInternational audienceModern embedded systems tend to use multiple cores or processors for proces...
International audienceThis paper deals with load balancing and efficient memory usage for homogeneou...
This report provides memory-aware heuristics to schedule tasks graphs onto heterogeneous resources, ...
Although numerous electronic devices are nowadays able to play video contents in real time and offer...
This paper presents a constructive algorithm for memory-aware task assignment and scheduling, which ...
International audienceA now-classical way of meeting the increasing demand for computing speed by HP...
Increasing interest in the high-volume high-performance embedded processor market motivates the stan...
Hardware accelerators, such as GPUs, now provide a large part of the computational power used for sc...
A now-classical way of meeting the increasing demand for computing speed by HPC applications is the ...
International audienceIn this paper, we present a new tri-criteria scheduling heuristic for scheduli...
International audienceScheduling in High-Performance Computing (HPC) has been traditionally centered...
The processor speeds continue to improve at a faster rate than the memory access times. The issue o...
Achieving optimal throughput by extracting parallelism in behavioral synthesis often exaggerates mem...