Theory and characterization of random defect formation and its implication in variability of nanoscale transistors

Over the last 50 years, carrier transport has been the central research topic in the semiconductor area. The outcome was a dramatic improvement in the performance of a transistor, which is one of the basic building blocks in almost all the modern electronic devices. However, nanoscale dimensions of current transistor following Moore’s law have shifted the spotlight from carrier transport towards the reliability and variability constraints. Modern transistors operate at a high electric field. They also use small metal gates and high-κ gate dielectric. Therefore, these transistors regularly suffer from process variations due to statistical variation in metal grain orientations at the gate, number of dopants in the substrate, thickness of the dielectric, etc. In addition to these ‘time-zero’ variation sources, presence of high oxide electric field and use of high-κ materials as dielectric (like silicon oxynitride and hafnium-based materials) strains the chemical bonds in the bulk and interface of the amorphous dielectric. As a result, defects are formed within a transistor, which leads to ‘time-dependent’ variation. Taken together, these ‘time-zero’ and ‘time-dependent’ phenomenon cause variation in transistor parameters (e.g., threshold voltage, mobility, sub-threshold slope, drain current) – which eventually lead to the IC failure, when the variation goes beyond a certain pre-defined limit. In this thesis, a physical model is developed to understand the defect formation at the dielectric/substrate interface of a transistor (a phenomenon, generally known as Negative Bias Temperature Instability), which is one of the major scaling concerns in current transistors. The time dynamics of interface defect generation is captured within a Reaction-Diffusion framework and hence compared with the characteristic experimental signatures measured over a wide range of supply voltage, temperature, materials within the dielectric, and channel strain. This comprehensive analysis further establishes the subtleties in interface defect characterization using modern techniques and also explains the intricacies for analyzing the impact of defect generation at circuit level. More importantly, the study with interface defects has identified the presence of self-compensation in advanced CMOS technology. Later, such self-compensation is shown to be generally applicable to many sources of ‘time-dependent’ and ‘time-zero’ variabilities. Design of such variation-resilient transistor may reshape how circuits are designed and evaluated currently for handling process-induced (time-zero) and temporal (time-dependent) variations – which is one of the grand challenges for continuing transistor scaling following Moore’s law