Process variation and thermal aware circuit design and test for nanoscale technologies

For more than three decades, aggressive scaling of transistor dimensions has been successful in achieving higher performance and increased functionality in CMOS IC technology. However, the increasing contribution of leakage power has been a major problem. Moreover, due to higher and non-uniform die temperatures caused by increasing power consumption, thermal aware circuit design has become essential in order to improve the robustness and thermal stability of circuits. Furthermore, as the process parameters (such as channel length, width, oxide thickness, number and location of dopant atoms) suffer large fluctuations due to limitations in the fabrication process and shrinking device geometries in scaled technologies, the robustness of circuits has degraded significantly. As a result, process variation aware circuit design has become crucial to improve parametric yield. In this research, we first address burn-in test where increased voltages and temperatures are applied to weed out defective devices. Due to the strong temperature dependence of leakage, leakage control during burn-in is required for thermal stability and thermal runaway prevention. We developed two circuit design techniques that ensure thermal stability during burn-in test under process parameter variations. Second, a detailed thermal analysis is performed on the performance, robustness and stability of embedded cache memories (such as SRAM and eDRAM). Finally, two process variation sensors are developed in order to characterize local random process variations for improved yield and process optimization. By utilizing sub-threshold region of operation, both sensors feature ultra-low power and high sensitivity without the need for any bias circuitry