Carbon nanotube transistor and its application

Single-walled carbon nanotubes (SWNTs) have attracted great attention during recent years due to prototypical 1D system and potential high performance materials to extend the capabilities of electronics, such as ballistic transparent, high current capability, low power dissipation, and flexible properties. Meanwhile, integration SWNT-FETs into integrated circuits has been hindered by uncontrolled variations. The device-to-device yield variations comes from a non-uniformity of diameter and chirality of SWNTs, variation of contact resistance, and interaction individual SWNTs with gate oxide and the surrounding environments. My researches have been focusing on developing reliable SWNT-FETs, and integrating individual devices into transparent electronics and high speed transistor. To exploit/achieve the high performance of SWNT-FETs, we proposed the following three techniques; (1) High k dielectrics films have been used as passivation and thin gate dielectric layers. (2) Electrical burning is executed to remove metallic nanotubes in channel, improving Ion/Ioff ratio for transistor. (3) Technique for realizing aligned SWNT arrays on quartz substrates is utilized to place SWNTs into a specific area for the active channel layer. The advanced three techniques are applied to fully transparent SWNT-TFTs and high speed devices. A study of integrating the transparent TFTs based on aligned SWNTs array is achieved. Representative SWNT-TFTs exhibit high performance p-type transistor characteristics with ∼83% transparency over the visible wavelength range. Furthermore, well-aligned SWNT-TFTs are composed of active channel for high speed transistors, presenting high mobility and sub-micron integration. The cut-off frequency of 2 GHz for RF SWNT-TFTs is observed