Automatic high-level functional test generation for microprocessors

In manufacturing testing, functional tests are known to detect unique defects that structural tests cannot detect. For microprocessor testing, high-level functional tests which are generated in the form of instruction sequences are often used instead of gatelevel functional tests due to the computational complexity of the gate-level test generation process. Traditionally, instruction sequences generated for design verification and random or pseudo-random instruction sequences are used as high-level functional tests. However, it is known that they cannot achieve high gate-level fault coverage. In this thesis, we propose a methodology for generating high-level functional tests with high fault coverage in an automated way. In our method, a microprocessor is partitioned into modules based on its RTL description, and the modules are targeted separately for test generation. Since the modules can be partitioned further into submodules if necessary, our method is scalable and applicable to large microprocessors. In our method, useful instructions and instruction subsequences that are likely to increase the fault coverage for each module are identified using high-level metrics we develop. They are then used to generate the final test sequence for the module. We develop different metrics for datapath and non-datapath modules, considering their characteristics, and tailor the test generation process to the type of module being considered. Since most of the simulations during the test generation process are performed at the RTL, our method is less time consuming than methods based on gate-level simulation. Our method is applied to the picoJava-II microprocessor from Sun Microsystems that is one of the largest microprocessors available in public domain