Process -tolerant CMOS circuit and system design

As the CMOS technology continues to scale down, power dissipation and robustness of a circuit with respect to process variations poses major design challenges in the nano-scale regime. In order to efficiently address these issues we need an integrated circuit-technology-architectural optimization approach to IC design under process variation. In this thesis, first, we develop a parametric yield enhancement technique for pipelined circuits. We propose analytical models to estimate yield for a pipelined design based on delay distributions of individual pipe stages. A statistical methodology is developed to optimally design a pipeline circuit for enhanced yield under an area constraint. Conventionally higher product yield indicates higher profit and/or revenue for the manufacturer. However, power and performance of a design are crucial for today\u27s semiconductor products. We propose a price-weighted yield metric as a better design optimization objective function under process variation. Using this price-aware design metric we developed a statistical design methodology to improve the profit of a design considering speed binning. Second, we study circuit optimization techniques for double gate FinFETs with independent gates (separate contacts to back and front gates). Independent control of front and back gate in double gate (DG) FinFET devices can be used to merge parallel transistors in non-critical paths to reduce the effective switching capacitance and hence dynamic power. Third, at the architectural level, we propose mixed-clock architecture based on GALS (Globally Asynchronous Locally Synchronous) design paradigm as the right choice for robust low power architecture. The proposed architecture can provide required performance at different process corners and operating conditions consuming the right amount of power for processing a set of real-time algorithm-specific tasks