Power and yield -aware design and test of nano-scale CMOS circuits

Over the last few decades, semiconductor industry has been fueled by exponential growth in computing power resulting from aggressive miniaturization of device geometry. As device integration and design complexity increase drastically with technology scaling, design and test professionals face major challenges. Leakage current increases exponentially with scaling. Increasing power dissipation and power density have also emerged as important design considerations and major barrier to scaling. Moreover, process parameter variations pose a major yield concern. In my doctoral research, I have addressed some of the major challenges in design and test of nanoscale VLSI systems. I have developed efficient design techniques to reduce system power in both standby and active mode while maintaining performance. Application of these techniques to architectural and logic-level of design abstraction has been addressed. To improve test cost and confidence. I have considered developing design techniques, which are low power and at the same time, testable. Finally. I have explored a novel defect-based-test solution to test CMOS circuits using the dynamic supply current. I have proposed wavelet transform based current signature analysis for efficient failure detection in digital and analog circuits and fault localization in digital circuits