Process development and characterization of planar self -aligned double -gate MOSFETs using epitaxial lateral overgrowth (ELO) and vertical seed ELO (VELO) techniques

Double-gate MOSFETs have the most ideal device structure, and are drawing the attentions of researchers due to their scalibility. Devices down to 20–30 nm in gate length with insignificant short channel effects are expected according to the previous theory and simulation works. The self-alignment of the top and bottom gates is proved to be critical in circuit performance. And the planar structure is the most promising one to meet the channel thickness requirement. However, a reliable planar self-aligned double-gate MOSFET process has yet been fully developed. The processes in the literature showed little or none electrical results, especially the subthreshold characteristics to prove their feasibility. In this work, a new planar self-aligned double-gate MOSFET process using epitaxial lateral overgrowth (ELO) and vertical seed ELO (VELO) techniques is proposed. To implement this new process in our laboratory environment, two simplified versions of the entire process were used. The first simplified process proved the feasibility and scalibility of the new process. Several critical techniques, such as a surrounding polysilicon gate deposition and VELO growth, are successfully developed. The second simplified process was used to fabricate real planar self-aligned double-gate MOSFETs. Submicrom P- and N-planar self-aligned double-gate MOSFETs are successfully fabricated. The electrical characterization showed double-gate MOSFET characteristics clearly. Near ideal subthreshold slope and low leakage current, which have not been shown by the previous processes, were measured. These devices are the first successfully fabricated planar self-aligned double-gate MOSFETs with VELO and in-situ doped source/drain (S/D). VELO can be grown symmetrically to form the S/D, and allow some process improvements, such as thicker sidewall spacers. In-situ doped S/D can achieve sharper S/D doping profile, which is necessary for the modern device technology. Further improvements and recommendations for implementing this process in real CMOS circuit fabrications are also discussed