Low power methodology for digital signal processing and multimedia communications

Low-power design can be addressed at different levels of design abstraction such as algorithm, architecture, logic, circuit, device, and system. This research presents low power design methodologies at architecture and system level. First, we present methodologies to reduce the implementation complexity of DSP systems. Low complexity design can be obtained by reducing the dynamic range of computation and reusing fundamental computations in a re-organized order. We propose graph theoretic techniques to reduce computational complexity. The efficiency of the proposed method is presented in the frame work of FIR filter implementation even though it can be applied to any problem related to MCM (Multiple Constants Multiplications) such as FFT and DCT. Multiplierless implementation with minimal computation complexity is suggested by the proposed approach. However, such low-complexity techniques suffer from irregular structure that may be associated with more complex interconnects. In scaled technology, communication cost of interconnect increases becoming comparable to computation cost. Hence, there is a need to mitigate the interconnect complexity efficiently. We propose an architecture synthesis technique which is incorporated with floorplanning. Using the proposed techniques, we obtain a layout-friendly implementation with minimal interconnect cost as well as minimal internal computation complexity. Second, we present a system level approach for multimedia system design. In hand-held multimedia applications, energy efficiency is important to enhance the mission-life-time of devices. We propose an energy-aware system to transmit an image with minimum energy dissipation. Energy-aware controller plays the key role to enhance energy efficiency based on simple performance and power modelling of each communication blocks