Algorithmic and architectural low -power techniques for digital signal processing and wireless communication applications

Many digital signal processing (DSP) and wireless communication applications utilize sophisticated algorithms, and realizing these algorithms using VLSI technology poses significant challenges due to high computational complexity or inherent complications of the algorithms, especially when designers are constrained with power consumption. We present algorithmic and architectural low-power techniques for several DSP algorithms. At the algorithmic level, we focus on reducing computational complexity. In low-complexity digital FIR filtering, common subexpression sharing and the use of differential coefficients are explored and two new techniques have been developed to reduce computational redundancy. Sphere decoding is at the heart of the maximum-likelihood detection in a multi-antenna system. We reduce complexity of the sphere decoding by proposing a new detection ordering scheme and incorporating lattice boundary awareness. At the architectural level, we propose a low-power VLSI architecture of a polyphase channelizer. A computationally efficient structure is derived. Efficient quantization of filter coefficients and complexity reduction in the polyphase matrix further reduce the power consumption. Also, we address the design of sigma-delta modulators with arbitrary transfer functions by proposing a genetic algorithm based search engine. Design examples show that the proposed method can effectively search for solutions with different characteristics and trade-offs. In the third part, we take an algorithm/architecture co-optimization approach for interconnect-aware synthesis of (3, k)-regular low-density parity-check (LDPC) codes. We integrate the LDPC code synthesis and its decoder floorplanning into a joint-optimization framework. With small or negligible degradation in bit error rate, interconnect cost such as routing congestion can be significantly reduced