Low-power high-performance SOI circuit design

This thesis studies double-gate fully-depleted (DGFD) SOI and 3-D integration circuit design. For DGFD SOI, we study how the added back-gate, with different back-gate oxide thicknesses, affects circuit performance, power dissipation, and reliability. Our analyses over different technology generations using MEDICI device simulator show that DGFD SOI circuits have significant advantages in driving high output load. DGFD SOI circuits also show excellent ability to control leakage current. However, for low output load, no gain is obtained for DGFD SOI circuits. Also, it is necessary to optimize the back-gate oxide thickness for optimum leakage current. We start our study of 3-D integration with a multiplier example to gain a basic understanding of the impact of new integration concept on physical design and circuit performance. We then present a stochastic 3-D interconnect model and study the impact of 3-D integration on circuit performance and power consumption. We show that 3-D structures effectively reduce the number of long delay nets, significantly reduce the number of repeaters, and dramatically improve circuit performance. With 3-D integration, circuits can be clocked at frequencies much higher (double or even triple) than 2-D. Finally, we combine the two new technologies, and study how DGFD and 3-D SOI circuits can better meet the performance and power dissipation requirements. Results show that DGSOI circuits and 3-D integration can be a viable solution to the future technology generations