WAFER SCALE INTEGRATION OF CONFIGURABLE, HIGHLY PARALLEL PROCESSORS

Integrated circuit size (and hence complexity) is limited by the fact that chips created using current design techniques will not function correctly in the presence of even a single circuit defect. This research examines the problem of constructing chips up to the size of the wafer (wafer scale integration) that operate correctly despite the occurrence of such flaws. We concentrate on a particular family of parallel processors, configurable, highly parallel (CHiP) processors. The key problem in the implementation of wafer scale integration is structuring the wafer so that only the functional PEs are connected together. A methodology, the two level hierarchy, that efficiently and economically solves the structuring problem for CHiP processors is presented. The principle elements are the use of column exclusion with high yield building blocks that contain redundant components. This approach limits the performance degradation due to structuring and allows the structuring problem to be solved with tractable computational effort. Since the yield of building blocks must be high for the two level hierarchy to be a practical approach, yield phenomena are investigated in detail. A model of the integrated circuit manufacturing process is developed that predicts circuit yield and the probability distribution of manufacturing defects. These results are applied to the analysis of parallel processors in which several PEs occupy a single chip. In addition, they are used to design the building blocks meeting the requirements of the column exclusion strategy. It was shown that these building blocks can be assembled into a wafer scale CHiP processor. With current technology, it is possible to fabricate a wafer scale system with 250 to 300 PEs. This represents a truly large parallel machine. Furthermore, this machine is highly robust to faults occurring during the machine\u27s lifetime, consumes a manageable amount of power and can be efficiently tested. Although the techniques for implementing wafer scale integration were developed for CHiP processors, they can be applied to other system composed of uniform parts