Automated Generation of Instruction Set Simulator from Specification

International audienceWe present here an architecture compiler, namely a software that takes as input the description of a processor architecture as it is available from the vendors on their web site, and generates an instruction set simulator for that processor, which can be readily integrated into a simulation framework. This architecture compiler extracts relevant information from the .pdf file, translated into an XML specification. After further XML transformations, the C++ code of the simulator is finally generated. The paper details the approach and the results for the ARM Version 7 processor, that is suitable for other architectures as well