A model of a message-passing network is used to analyze the behavior of three implementations of the Chandy-Misra-Bryant parallel simulation algorithm. The characteristics of the model, the organization of the logical processes that constitute the simulator and the characteristics of the host parallel computer have a definite influence on the achieved performance, measured in terms of speedup. Large, loaded models help CMB to synchronize with a minimum overhead, efficiently exploiting the available parallelism. Mapping several LPs onto each processor achieves a better use of the available processing power, because while a LP is blocked (synchronizing) others can use the CPU. However, it is not convenient to map too many LPs onto each proces...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering, 1995.Includes...
The Chandy-Misra-Bryant (CMB) model has been applied to logic simulation of synchronous sequential c...
A suite of benchmarking routines testing communication, basic arithmetic operations, and selected ke...
There are a lot of 386/486/Pentium-based personal computers (PCs) out there. They are affordable, re...
Parallel computers constructed using conventional processors offer the potential to acheve large imp...
This paper examines methods for synchronisation and communication between tasks in highly parallel a...
This paper considers the suitability of SPED, a synchronous parallel discrete event simulator, for t...
Performance gains in computer design are quickly consumed as users seek to analyze larger problems t...
A systematic procedure is developed for exploiting the parallel constructs of computation in a highl...
During the design phase of modern digital and mixed signal devices, simulations are run to determine...
With traditional event list techniques, evaluating a detailed discrete event simulation model can of...
Simulation of circuits and faults is an essential part in design and test validation tasks of contem...
With the proliferation of parallel computing, parallel computer-aided design (CAD) has received sign...
Call number: LD2668 .T4 CMSC 1989 V67Master of ScienceComputing and Information Science
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering, 1995.Includes...
The Chandy-Misra-Bryant (CMB) model has been applied to logic simulation of synchronous sequential c...
A suite of benchmarking routines testing communication, basic arithmetic operations, and selected ke...
There are a lot of 386/486/Pentium-based personal computers (PCs) out there. They are affordable, re...
Parallel computers constructed using conventional processors offer the potential to acheve large imp...
This paper examines methods for synchronisation and communication between tasks in highly parallel a...
This paper considers the suitability of SPED, a synchronous parallel discrete event simulator, for t...
Performance gains in computer design are quickly consumed as users seek to analyze larger problems t...
A systematic procedure is developed for exploiting the parallel constructs of computation in a highl...
During the design phase of modern digital and mixed signal devices, simulations are run to determine...
With traditional event list techniques, evaluating a detailed discrete event simulation model can of...
Simulation of circuits and faults is an essential part in design and test validation tasks of contem...
With the proliferation of parallel computing, parallel computer-aided design (CAD) has received sign...
Call number: LD2668 .T4 CMSC 1989 V67Master of ScienceComputing and Information Science
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering, 1995.Includes...
The Chandy-Misra-Bryant (CMB) model has been applied to logic simulation of synchronous sequential c...