Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faults

International audienceFine-grained disabling and reconfiguration of hardwareelements (functional units, cache blocks) will become economicallynecessary to recover from permanent failures, whoserate is expected to increase dramatically in the near future.This fine-grained disabling will lead to degraded performanceas compared to a fault-free execution.Until recently, all static worst-case execution time (WCET)estimations methods were assuming fault-free processors, resultingin unsafe estimates in the presence of faults. The firststatic WCET estimation technique dealing with the presenceof permanent faults in instruction caches was proposed in [1].This study probabilistically quantified the impact of permanentfaults on WCET estimates. It demonstrated that the probabilisticWCET (pWCET) estimates of tasks increase rapidly with theprobability of faults as compared to fault-free WCET estimates.In this paper, we show that very simple reliability mechanismsallow mitigating the impact of faulty cache blocks on pWCETs.Two mechanisms, that make part of the cache resilient to faultsare analyzed. Experiments show that the gain in pWCET forthese two mechanisms are on average 48% and 40% as comparedto an architecture with no reliability mechanism