Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence (Invited)
- Maneux, Cristell
- Chhandak, Mukherjee
- Deng, Marina
- Dubourg, Maeva
- Réveil, Lucas
- Bordea, Georgeta
- Lecestre, Aurélie
- Larrieu, Guilhem
- Trommer, Jens
- Breyer, Evelyn,
- Slesazeck, Stefan
- Mikolajick, Thomas
- Baumgartner, Oskar
- Karner, M.
- Pirker, David
- Stanojevic, Zlatan
- Atienza, David
- Levisse, Alexandre
- Ansaloni, Giovanni
- Poittevin, Arnaud
- Bosio, Alberto
- Deleruyelle, D.
- Marchand, Cédric
- O'Connor, Ian
Publication date
December 2021
DOI Publisher
Institute of Electrical and Electronics Engineers (IEEE)Abstract
International audienceThis paper presents the set of simulation means used to develop the concept of N2C2 (neural network compute cube) based on a vertical transistor technology platform. On the basis of state-of-the-art junctionless nanowire transistors (JLNT), TCAD simulation, compact modeling and EM simulation are leveraged through a Design- Technology Co-Optimization (DTCO) to achieve innovative 3D circuit architectures. Further, System-Technology Co-Optimization (STCO) implications on 3D NN system architecture are explored
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