Combining watchdog processor with instruction cache locking for a fault-tolerant, predictable architecture applied to fixed-priority, preemptive, multitasking real-time systems

[EN] Control flow monitoring using a watchdog processor is a well-known technique to increase the dependability of a microprocessor system. Most approaches embed reference signatures for the watchdog processor into the processor instruction stream. These signatures contain the information required to detect control flow errors during program execution by the main processor. This paper proposes an architecture that offers both fault-tolerance and dynamic cache locking combined. This combination is achieved taking advantage of the fact that watchdog processor signatures are inserted along the program code. Then cache locking information is incorporated into these signatures. And also the required circuitry to inform the cache controller whether to lock or not the instructions fetched by the main processor is added into the watchdog processor. With this approach both fault-tolerant and real-time features are supported by the same hardware, therefore saving room on the silicon die or FPGA size. Results from experiments show that in most cases this approach reaches the same performance than previous, hardware-costly proposals.This work was partially funded by the Plan Nacional de I+D, Comision Interministerial de Ciencia y Tecnologia (FEDER-CICYT) under the project HAR2017-85557-P and Agencia Estatal de Investigacion under the project DPI2016-80303-C2-1-P.Martí-Campoy, A.; Rodríguez-Ballester, F. (2019). Combining watchdog processor with instruction cache locking for a fault-tolerant, predictable architecture applied to fixed-priority, preemptive, multitasking real-time systems. IEEE. 259-265. https://doi.org/10.1109/ETFA.2019.886916825926