A Fully Fledged HDL Design Flow for In-Memory Computing with Approximation Support

Most computers today are based on the von Neumann architecture introduced by John von Neumann in 1945 which suffers from the von Neumann bottleneck. However, recently, new applications have emerged, such as deep learning and IoT. These applications pose their own challenges and requirements. In particular, due to the von Neumann bottleneck, the classical von Neumann architecture becomes very inefficient for such use-cases. Recently, ReRAM, a resistance based storage device, is emerging. ReRAM is especially appealing due to its inherent in-memory computation capabilities. In addition, ReRAMs low power consumption, scalability and fast switching capabilities make it an excellent candidate for a technological foundation for edge devices and IoT. In order to overcome the von Neumann bottleneck, an architecture for the PLiM~computer has been proposed. In addition to the control logic, the core of the PLiM computer architecture are the ReRAM arrays, which are used as storage and computational unit. In this thesis, we propose a design flow for in-memory computing and the PLiM computer architecture with support for Approximate Computing. First, we present approximation techniques, which are applicable for arbitrary circuits. Then, we introduce LiM-HDL - a HDL for the high-level specification of PLiM programs. As LiM-HDL is compatible with Verilog, it is easy to integrate into existing architectures and has a low hurdle to entry. Then, after transforming LiM-HDL to a graph, we propose graph-based synthesis algorithms. Finally, we propose additional optimization techniques, which are based on our previously presented approximate computing techniques and a novel graph structure which we call m-AIGs