Hardware acceleration for real time processing systems

This Master Thesis presents different Hardware acceleration algorithms and its benefits compared to the software implementation. The proposed algorithms are implemented on Xilinx ZYNQ-7000 series XC7Z020 SoC using High-Level-Synthesis (HLS) tool. With todays System-on-Chips from Xilinx or Intel, a process can be chosen to be implemented in the Programmable Logic or in the Processing System. In order to have a better acceleration factor, different approximate and accurate adders and multipliers were instantiated in Verilog, synthesized and simulated using Vivado and finally they were compared between each other to see if they really offer benefits or not. In the case of approximated adders, they showed very promising results for the application written in this Thesis. On the other hand, approximated multipliers exhibited worse results than the accurate ones