Exploring Simple Core Organizations for Near-Data Processing

The limitations of DRAM technology in terms of energy consumption and Bandwidth poses a serious problem to the design of faster processing units. Conventional CPUs have increased their computational abilities faster than the available bandwidth to memory. This has led to the creation of more and more sophisticated systems to extract the most out of the limited DRAM capabilities. To further provide faster and more efficient computational solutions, new ways of computer design have to be explored. One promising re-emerging approach is Near-Data Processing, that moves the computational capabilities close to memory, thus reducing the movement of data. This thesis studies the design space of simple cores, that could be used in future implementations of Near-Data Processing. It explores the cost of address translation and the need for data movement for a set of promising Near-Data Processing workloads