Add to ORKGThe proposed energy efficient SRAM cell is designed with 11 Transistors and implemented in 45nm CMOS technology. The separate read circuit reduces the read power and improves the read stability. The cell is compared with 4 other cells in terms of power, stability, temperature, supply and threshold voltage, read/write behaviours in the PVT conditions. The robustness of the cells are evaluated with different PVT variations. The 32Kb array is also been simulated for power, dealy and stability
Cell stability and area are among the major concerns in SRAM cell designs. This paper compares the p...
The growth of Static Random Access Memory (SRAM) based cache memory is immensely sweeping for the cu...
In digital systems memory arrays are forming an integral building block. There are various aspects t...
Many WSN applications are highly used in military surveillance, environment monitoring, health mon...
This book features various, ultra low energy, variability resilient SRAM circuit design techniques f...
The SRAM based cache memory has been radically increasing in low power applications. The on-chip dat...
In the last decade, the development of embedded on-chip SRAM memories has been radically increasing....
Stability of a Static Random Access Memory (SRAM) cell is an important factor when considering an SR...
Memory arrays are an essential building block in any digital system. SRAM is a device that has infil...
In this work, a data-dependent feedback-cutting–based bit-interleaved 12T static random access memor...
Assist (DARWA) technique. The E2VR11T cell comprises 11 transistors and operates with single-ended r...
The sensor network has become an important aspect in the day today life because of its wide range of...
The low power and high performance Static Random Access Memory (SRAM) is the main constraint in mode...
The primary aim of electronics is to design low power devices due to the frequent usage of powered w...
SRAM cell is the basic memory devices which is made from the combination of Flip Flop and registers ...
Cell stability and area are among the major concerns in SRAM cell designs. This paper compares the p...
The growth of Static Random Access Memory (SRAM) based cache memory is immensely sweeping for the cu...
In digital systems memory arrays are forming an integral building block. There are various aspects t...
Many WSN applications are highly used in military surveillance, environment monitoring, health mon...
This book features various, ultra low energy, variability resilient SRAM circuit design techniques f...
The SRAM based cache memory has been radically increasing in low power applications. The on-chip dat...
In the last decade, the development of embedded on-chip SRAM memories has been radically increasing....
Stability of a Static Random Access Memory (SRAM) cell is an important factor when considering an SR...
Memory arrays are an essential building block in any digital system. SRAM is a device that has infil...
In this work, a data-dependent feedback-cutting–based bit-interleaved 12T static random access memor...
Assist (DARWA) technique. The E2VR11T cell comprises 11 transistors and operates with single-ended r...
The sensor network has become an important aspect in the day today life because of its wide range of...
The low power and high performance Static Random Access Memory (SRAM) is the main constraint in mode...
The primary aim of electronics is to design low power devices due to the frequent usage of powered w...
SRAM cell is the basic memory devices which is made from the combination of Flip Flop and registers ...
Cell stability and area are among the major concerns in SRAM cell designs. This paper compares the p...
The growth of Static Random Access Memory (SRAM) based cache memory is immensely sweeping for the cu...
In digital systems memory arrays are forming an integral building block. There are various aspects t...