Applying architectural parallelism in high-performance network subsystems

Gigabit per second (Gbps) bandwidths can now be delivered by networks to workstation hosts. This dissertation addresses the problem of delivering this bandwidth through the network subsystem of a host workstation to a user\u27s application. A central focus is the identification and removal of performance bottlenecks. The two approaches which I have explored are the optimization of a single data path and the combination of multiple data paths between the network and applications running on the workstation. Asynchronous Transfer Mode (ATM) Segmentation and Reassembly (SAR) was initially thought to be a bottleneck. I designed a scalable hardware architecture which is host-independent and able to perform SAR at rates of over 1 Gbps. I have implemented it in a 160 Mbps host interface for the IBM RISC System/6000 workstation and at 640 Mbps for HP 9000/700 workstations. It is now clear that relatively simple hardware can perform SAR at high speeds, and that the overall system bottlenecks lie elsewhere, such as the host\u27s memory, I/O subsystems, and operating system. Bottlenecks can also be removed by using parallel data paths. These paths can be transparently combined to obtain a virtual resource that is indistinguishable from a single, higher performance data path. The techniques used are similar to the striping concept which has been applied to disk subsystems. I developed a precise terminology for describing striping within a networking context and performed a systematic analysis of striping at various layers in a networking protocol stack. My results using these two approaches have advanced our understanding of architectural techniques for designing and implementing network subsystems. The impact of the results is already widespread and will further increase as ATM becomes a dominant network technology