High-efficiency and high-usability heterogeneous hardware acceleration with FPGAs

The exploding complexity and computation efficiency requirements of applications are stimulating a strong demand for hardware acceleration with heterogeneous platforms that may contain CPUs, GPUs, FPGAs, ASICs, and other customized accelerators. Among these processors and hardware accelerators, field-programmable gate arrays (FPGAs) provide flexible programmability, low computation latency, as well as fine-grained parallel processing capability, and have demonstrated outstanding performance and flexibility in many applications and scenarios. However, a high-quality FPGA design is very hard to create and optimize as it requires FPGA expertise and a long design iteration time. In contrast, software applications are typically developed in a shorter development cycle, with high-level languages like Python, which is at a much higher level of abstraction than all existing hardware design languages. In this dissertation, we will first look into the basics of high-efficiency and high-usability FPGA accelerators in the heterogeneous hardware acceleration systems, including categories of accelerators, system architecture, design methodology, and so on. Secondly, we will discuss the optimization of heterogeneous systems that enables CPU-FPGA collaborative computing and improves system performance. Thirdly, we will look into our proposed high-level programming languages and optimization flows of FPGA accelerators, including language design, compiler design, optimization techniques, and so on. Finally, we will discuss how the proposed high-level programming and optimization flow can be used to program and optimize heterogeneous systems